1. Field of the Invention
The present invention relates to an address generating and decoding apparatus included in a microprocessor, a digital signal processor and the like.
2. Description of the Related Art
In a microprocessor, a digital signal processor and the like, when accessing a memory storage unit (MSU), a memory address needs to be calculated. Generally, such a memory address is generated by the addition of two addresses such as a base address and a displacement. Also, the memory address is decoded by a decoder to generate a decoding signal for the MSU.
A prior art address generating and decoding apparatus uses a partial address generating and decoding method. That is, a plurality of partial decoding signal generating units, each for generating one of the partial decoding signals, are connected in parallel. Also, each of the partial decoding signal generating units includes an adder, for adding a part of a first address to a part of a second address, a carry look ahead circuit, and a decoder for decoding the output of the adder. A carry output signal of one of the partial decoding signal generating units on the downstream side is supplied to the adder and the carry look ahead circuit of another of the partial decoding signal generating units on the upstream side. This will be explained later in detail.
In the above-mentioned prior art address generating and decoding apparatus, however, a carry signal is propagated through the adders of the partial decoding signal generating units and each adder carries out an addition operation using the carry signal from the partial decoding signal generating units on the downstream side in addition to the first and second addresses. In other words, the operation of the partial decoding signal generating units on the upstream side is reduced in comparison to that of the partial decoding signal generating units on the downstream side, thus reducing the operation speed of the entire apparatus.